The invention relates to a signal processor comprising a program memory for storing compressed program instruction words, and a decoder for decoding the compressed program instruction words which are used in decoded form to control functions of the signal processor.
Digital signal processors (DSP) are special microprocessors having a high computing speed, whose instruction sets and architectures are tuned to special requirements in the field of digital signal processing and which are particularly used for converting complex algorithms in real time. For example, signal processors are used in the field of mobile radio according to the GSM standard where they are used in mobile radios (mobile stations) or base radio stations for converting complex speech processing algorithms. Further fields of application are, for example, audio, video, medical and automotive technology.
Customary signal processors have a program memory in which program instructions are stored in compressed form (ie in encoded form), which, when called, leads to parallel execution of different signal processing operations, for example, simultaneous execution of two data transfers over two different data buses, two address computations, one arithmetic/logic operation and one multiplication. Examples of customary signal processors are the Philips PCF 5083 (KISS), the AT&T DSP 16xx and the Texas Instruments TMS 320. The program instructions are stored as 16-bit words in program memories in these signal processors. In the case of a decoding (decompression) by means of a decoder, the compressed 16-bit program instruction words are converted (expanded) to program instruction words having a larger word size which depends on the complexity of the signal processor used. A typical word size for the expanded program instruction words lies between 32 and 128 bits. A call of program instructions during a program run causes a parallel signal processing to be realized, in which the individual bits of the decoded program instruction words are applied to respective control lines of the signal processor. Compared to storing the program instructions in uncompressed form, the storing of the program instructions by means of compressed program instruction words leads to a reduction of the memory space requirement and is possible, because the number of the various theoretically possible program instruction words is limited accordingly.
The decoding of program instruction words in such signal processors is effected by a hardwired decoder which performs the decoding by logical operations. Based on the compression of the program instruction words and compared to the theoretical maximum of different program instruction words, only an accordingly reduced number of different compressed program instruction words can be coded in the program memory. Combined with the use of a hardwired decoder, this leads to a restricted program instruction set (restricted parallel signal processing). In the example mentioned above, only 2.sup.16 different program instruction words or program instructions respectively, are possible with compressed program instruction words having 16 bits. In theory, 2.sup.32 . . . 2.sup.128 different program instruction words would be conceivable. Further program instructions linked with another combination of different signal processing operations, which program instructions would certainly be possible based on the given signal processor architectures, cannot be used for programming the signal processor. With special compute-bound applications, for example, with the conversion of the half rate CODEC or the enhanced full rate CODEC in the field of mobile radio (GSM), the predefined standard instruction set of the signal processor described above is not sufficient for an effective conversion of the respective complex signal processing algorithms in real time.